1. Field of the Invention
The present invention relates to a driving module and driving method, and more particularly, to a driving module and driving method charging subpixels with different charging orders in different frames, or charging subpixels with different charging periods in a same frame, to avoid charging inequality among the subpixels.
2. Description of the Prior Art
A liquid crystal display (LCD) device utilizes a source driver and a gate driver to drive pixels on a panel to display images. Since cost of a source driver is higher than that of a gate driver, in order to reduce number of source drivers, a pixel structure evolves from a single gate structure to a dual gate structure or a tri-gate structure. Taking the tri-gate structure as an example, for the same number of pixels, compared to the single gate structure, the tri-gate structure only has one-third as many data lines, and thrice as many scan lines for reducing the cost. However, since a gate driving signal has only a third of the conventional active cycle, a data line can only charge pixels with a third of the conventional charging time, and the pixels are likely charged insufficiently.
Please refer to FIG. 1, which is a schematic diagram of an LCD device 10 with a stripe tri-gate pixel structure in the prior art. For clear illustration, the LCD device 10 only includes a source driver 100, a gate driver 102, a timing controller 104, an LCD panel 106, data lines S1-Sm, scan lines G1-Gn and a pixel matrix Mat_S. The timing controller 104 utilizes a horizontal synchronization signal Hsync and an output enable signal Ena to control the source driver 100 and the gate driver 102, respectively, to generate data driving signals Sig_S1-Sig_Sm and gate driving signals Sig_G1-Sig_Gn, so as to charge the pixel matrix Mat_S. In the pixel matrix Mat_S, each pixel includes a red subpixel R, a green subpixel G and a blue subpixel B, and each subpixel includes a transistor and a capacitor, which are denoted by blocks for simplicity. In one cycle of the horizontal synchronization signal Hsync, the data driving signals Sig_S1-Sig_Sm charge a corresponding pixel, respectively. For example, in one cycle of the horizontal synchronization signal Hsync, the data driving signal Sig_S1 charges a pixel corresponding to the data line S1 and the scan lines G1-G3, i.e. a red subpixel, a green subpixel and a blue subpixel. Under such a situation, since charging period for a subpixel in the tri-gate structure is only a third of that of the single gate structure, the subpixels are likely charged insufficiently.
Please refer to FIG. 2, which is a schematic diagram of the LCD device 10 driving subpixels corresponding to the data line S1 in frames F1, F2. FIG. 2 indicates charging orders of the scan lines G1-Gn and corresponding subpixels thereof, and a waveform of the data driving signal Sig_S1 in horizontal synchronization cycles Hsync_C1, Hsync_C2. As shown in FIG. 2, since the data driving signal Sig_S1 has circuit RC delay, the data driving signal Sig_S1 needs a period to reach a settled state when the data driving signal Sig_S1 has polarity change. Besides, subpixels within the same horizontal synchronization cycle have the same charging period. As a result, for subpixels corresponding to the same horizontal synchronization cycle, a subpixel with the most prior charging order of the data driving signal Sig_S1 is charged insufficiently. For example, in the frame F1, the charging orders are scan lines G1→G2→G3 and subpixels R→G→B in the horizontal synchronization cycle Hsync_C1. Since the data driving signal Sig_S1 does not reach the settled state when charging the red subpixel R, the red subpixel R is charged less sufficiently compared to the green subpixel G and the blue subpixel B. Similarly, in the frame F2, since the red subpixel R is still the subpixel with the most prior charging order of the data driving signal Sig_S1 in the horizontal synchronization cycle Hsync_C1, the red subpixel R is still charged less sufficiently. By the same token, the red subpixels R corresponding to the scan line G1 and the data lines S1-Sm are all charged less sufficiently, causing the LCD device 10 to exhibit light and dark lines and color inequality due to charging inequality among subpixels.
Please refer to FIG. 3A and FIG. 3B, which are schematic diagrams of utilizing double gate pulses and overlap gate pulse to drive subpixels in the prior art, respectively. In order to eliminate charging inequality, the prior art utilizes the double gate pulses or the overlap gate pulse to pre-charge the subpixels, such that the subpixels are not charged unequally when the data driving signals charge the subpixels. As shown in FIG. 3A, compared to the driving method shown in FIG. 2, the double gate pulses pre-charges the subpixels before the horizontal synchronization cycle Hsync_D1, Hsync_D2, such that the LCD device 10 does not have light and dark lines and color inequality due to charging inequality among subpixels in the horizontal synchronization cycle Hsync_C1, Hsync_C2. Similarly, as shown in FIG. 3B, the overlap gate pulse pre-charges the subpixels before a third of the horizontal synchronization cycle Hsync_C1, i.e. charging period for a subpixel, such that the LCD device 10 does not have light and dark lines and color inequality due to charging inequality among subpixels in the horizontal synchronization cycle Hsync_C1, Hsync_C2.
However, driving methods of the double gate pulses and the overlap gate pulse in the prior art need extra pulses to avoid charging inequality, which increase power consumption and inconvenience. Thus, there is a need for improvement.